It is provided freely from the OSCI website at www. These are the skills that enable a great SystemC modeler. Not so obviously to some, the language needs to support concurrent simulation we will talk about this extensively later in the book.
The language must also support a series of additional productivity features. Any model needs to execute relatively swiftly.
A model is never fast enough, so what is fast enough. One can look at the requirements for model speed when used for common ESL purposes like early software development. No modeling language can make up for inefficient modeling practices.
As the reader may have guessed by now, developing a model is different than developing an application program. The difference is that in an ESL model, the 1. When a digital system is running, then many, many computations are running at the same time or are running concurrently. SystemC provides a simulation kernel to give this illusion of concurrency.
This feature, as well as several others, helps manage the complexity of the model. In addition, SystemC is supported by a large and growing ecosystem of commercial suppliers.
Some of these tools include integrated development environments IDEs , performance analysis tools, and lint tools to illustrate just a few. There are many more tools available from leading software tool vendors for a small fee. These tools come with varying degrees of support. Many of the groups using SystemC are large organizations that require ESLspecific productivity tools and technology as well as significant support. The last time we counted, the list was over 40 companies and growing.
The tools range from co-simulation with their HDL simulators to behavioral synthesis tools. The availability of graphic algorithms, DSP algorithms, and a plethora of other application libraries make the writing of initial models very easy. An extreme example is the use of an H. It must support the easy substitution of one communication implementation with another without changing the interface to that implementation.
You will then be equipped to charge into the brave new world of ESL and TLM modeling and to bring about significant changes in your organization, company, and the industry. This chapter presents an overview of the SystemC language elements.
Details are discussed in-depth in subsequent chapters. Despite our best efforts not to use any part of the language before it is fully explained, some chapters may occasionally violate this goal due to the interrelated nature of SystemC. This chapter briefly discusses the major components of SystemC and their general usage and interactions as a way of giving context for the subsequent chapters.
The following diagram, Fig. As a form of roadmap, we have included a duplicate of this diagram at the beginning of each new chapter. Bolded type indicates the topics discussed within that chapter. For the rest of this chapter, we will discuss all of the components within the figure that are outlined in bold; but first, we will discuss the mechanics of the SystemC development environment. The primary application area for SystemC is the design of electronic systems. However, SystemC also provides generic modeling constructs that can be applied to non-electronic systems1 Fig.
The download contains scripts and make files for installation of the SystemC library as well as SystemC source code, examples, and documentation. The install scripts are compatible with the supported operating systems, and the scripts are relatively straightforward to execute by carefully following the documentation.
At this time, the OS list is limited by the use of minor amounts of assembly code that is used for increased simulation performance in the SystemC simulation kernel.
For beginners, this OS and compiler list should be considered exhaustive. The flow for compiling a SystemC program or design is very traditional and is illustrated in Fig. Most other compilers will be similar. Each file set usually consists of two files, typically with standard file extensions. We use. Note that the compiler and linker need to know two special pieces of information. First, the compiler needs to know where the SystemC header files are located.
Second, the linker needs to know the location of the compiled SystemC libraries. This information is typically passed by providing an environment variable named 2. The downloadable examples available from our web site include a makefile setup for Linux and gcc. The resulting file is usually referred to as an executable, and it contains the SystemC simulation kernel and your design functionality.
The rest of you now have an overview of how to compile and run the code examples in this book as well as your own SystemC creations. Everyone is now ready to dive into the language itself. For some installations, dynamic libraries may also be referenced if using the SystemC Verification library. SystemC provides several hardware-oriented constructs that are not normally available in a software language; however, these constructs are required to model hardware.
This section looks at SystemC from the viewpoint of the hardware-oriented features. Global time is advanced within the kernel. SystemC provides mechanisms to obtain the current time and implement specific time delays. To support ease of 2. Since many applications in SystemC do not require a clock but do require a notion of time , the clock discussion is deferred to later chapters of the book.
Additionally, clocks do not add to the fundamental understanding of the language. By the later chapters, you should be able to implement the clock class yourself with the fundamentals learned throughout the book. SystemC provides hardware-compatible data types that support explicit bit widths for both integral and fixed-point quantities. Furthermore, digital hardware requires non-binary representation such as tri-state and unknowns, which are provided by SystemC.
Finally, hardware is not always digital. SystemC does not currently directly support analog hardware; however, a working group has been formed to investigate the issues associated with modeling analog hardware in SystemC. For those with immediate analog issues, it is reasonable to model analog values using floating-point representations and provide the appropriate behavior. SystemC provides several constructs for implementing hardware hierarchy.
Hardware designs traditionally use blocks interconnected with wires or signals for this purpose. For modeling hardware hierarchy, SystemC uses the module entity interconnected to other modules using channels. The hierarchy comes from the instantiation of module classes within other modules. Conceptually, a channel is more than a simple signal or wire. The ability to have several quite different channel implementations used interchangeably to connect modules is a very powerful feature. This feature enables an implementation of a simple bus replaced with a more detailed hardware implementation, which is eventually implemented with gates.
SystemC provides several built-in channels common to software and hardware design. These built-in channels include locking mechanisms like mutex and semaphores, as well as hardware concepts like FIFOs, signals and others. Finally, modules connect to channels and other modules via port classes. Simulators execute the code on a single physical processor. Even if you did have multiple processors performing the simulation, the number of units of concurrency in real hardware design will always outnumber the processors used to do the simulation by several orders of magnitude.
Consider the problem of simulating the processors on which the simulator runs. Simulation of concurrent execution is accomplished by simulating each concurrent unit. Each unit is allowed to execute until simulation of the other units is required to keep behaviors aligned in time.
In fact, the simulation code itself determines when the simulator makes these switches by the use of events. In other words, the simulator uses a cooperative multitasking model.
The simulator merely provides a kernel to orchestrate the swapping of the various concurrent elements, called simulation processes. SystemC provides a simulation kernel that will be discussed lightly in the last section of this chapter and more thoroughly in the rest of the book. This section has presented an overview of SystemC relative to a generic set of requirements for hardware design.
We will now give a brief overview of the constructs used to implement these requirements in SystemC. Each level of hierarchy represents a block. In Verilog, blocks are called modules and contain both interface and implementation in the same code.
Modules may contain other modules, processes, and channels and ports for connectivity. As indicated earlier, the SystemC simulation kernel schedules the execution of all simulation processes. Because the simulation kernel is the only caller of these member functions, they need no arguments and they return no value. From a software perspective, processes are simply threads of execution. From a hardware perspective, processes provide necessary modeling of independently timed circuits.
The simulation kernel invokes each of these processes. Therefore, they are never invoked directly by the user. The user indirectly controls execution of the simulation processes by the kernel as a result of events, sensitivity, and notification. Events are caused or fired through the event class member function, notify.
The notification can occur within a simulation process or as a result of activity in a channel. SystemC has two types of sensitivity: static and dynamic. Dynamic sensitivity lets a simulation process change its sensitivity on the fly. This process type is a thread process that has the requirement of being sensitive to a clock. Also, SystemC lets you define new data types for new hardware technology i.
These data types evaluate the performance of an algorithm when implemented in custom hardware or in processors without full floating-point capability. SystemC provides all the necessary methods for using hardware data types, including conversion between the hardware data types and conversion from hardware to software data types. Non-binary hardware types are supported with four-state logic 0,1,X,Z data types e. In SystemC, processes communicate using channels or events.
Processes may also communicate across module boundaries. Modules may interconnect using channels, and connect via ports. The powerful ability to have interchangeable channels is implemented through a component called an interface. SystemC provides some standard channels and interfaces that are derived from these base types. Interestingly, module interconnection happens programmatically in SystemC during the elaboration phase.
This interconnection lets designers build regular structures using loops and conditional statements. From a software perspective, elaboration is simply the period of time when modules invoke their constructor methods. It can appear rather intimidating since it shows almost all of the concepts within one diagram. In practice, a SystemC module typically will not contain all of the illustrated components.
Coordination among simulation processes is also accomplished through events. We will now give a brief initial overview of the SystemC simulation kernel that coordinates and schedules the communications among all of the components illustrated in Fig. A third, often minor, phase occurs at the end of execution; this phase could be characterized as post-processing or cleanup. This phase is characterized by the initialization of data structures, the establishment of connectivity, and the preparation for the second phase, execution.
The execution phase hands control to the SystemC simulation kernel, which orchestrates the execution of processes to create an illusion of concurrency. The illustration in Fig. After initialization, simulation processes are run when events occur to which they are sensitive.
The SystemC simulator implements a cooperative multitasking environment. Once started, a running process continues to run until it yields control. Several simulation processes may begin at the same instant in simulator time. In this case, all of the simulation processes are evaluated and then their outputs are updated. An evaluation followed by an update is referred to as a delta cycle. If no additional simulation processes need to be evaluated at that instant as a result of the update , then simulation time is advanced.
When no additional simulation processes need to run, the simulation ends. This brief overview of the simulation kernel is meant to give you an overview for the rest of the book.
Either suspend waiting or exit entirely. It is very important to understand how the kernel functions to fully understand the SystemC language.
We have provided an animated version of this diagram walking through a small code example at our web site, www. This manual is the definitive source about SystemC. We encourage the reader to use any or all of these resources during their study of SystemC to fully understand the simulation kernel.
We have attempted to be considerably briefer. The SystemC library provides integer, logic, and fixed-point data types designed for modeling hardware. The use of SystemC data types is not restricted to models using the simulation kernel; they may be used in non-simulation applications as other data types would be used. Though simulation models may be created using any of the available data types, the choice of data types affects simulation speed, synthesizability, and synthesis results.
Table 3. The beginner will want to become familiar with string from the STL. There are two SystemC logic vector types: 2-valued and 4-valued logic; and two SystemC numeric types: integers and fixed-point. All SystemC data types implement equality and bitwise operations. The SystemC arithmetic data types integer and fixed-point implement arithmetic and relational operations.
The SystemC data types allow single-bit and multi-bit select operations. The results of these select operations may be used as the source right-hand side or 3.
The SystemC logic vector types are intended to model at a very low level near RTL and do not implement arithmetic operations. They do implement a full range of assignment and logical operations, given some obvious restrictions. In addition to bit selection and bit ranges i. Reduction operations place the operator between all adjacent bits.
The two data types are a limited precision integer type, which has a maximum length of bits, and a finite precision integer type, which can be much longer. The native data types are optimized for the host processor instruction set and are very efficient. These data types are typically 8, 16, 32, or 64 bits in length. The SystemC integer data types are templated and may have data widths from 1 to hundreds of bits.
In addition to configurable widths, the SystemC integer data types allow bit selections, bit range selections, and concatenation operations. These data types provide large number support at the cost of speed. As a design evolves, fixed-point data types can provide higher fidelity modeling of the signal processing logic and can be used to provide a path to a synthesizable design.
The SystemC fixed-point data types Fig. Optional parameters provide control of overflow and quantization modes. Unlike other SystemC data types, fixed-point data types may be configured at compile time, using template parameters or at run time using constructor parameters. Regardless of how a fixed-point data object is created, it cannot be altered later in the execution of the program. The fixed-point data types have several easy-to-remember distinctions. Third, the past tense ed suffix to fix indicates a templated data type that must have static parameters defined using compile-time constants.
Author : Michael J. Author : H. Charles S. Author : Charles S. Stahel Publisher: Springer Reads. Author : W. We use cookies on our website to give you the most relevant experience by remembering your preferences and repeat visits. However, you may visit "Cookie Settings" to provide a controlled consent. Cookie Settings Accept All. Manage consent. Close Privacy Overview This website uses cookies to improve your experience while you navigate through the website. Out of these, the cookies that are categorized as necessary are stored on your browser as they are essential for the working of basic functionalities of the website.
We also use third-party cookies that help us analyze and understand how you use this website. These cookies will be stored in your browser only with your consent. You also have the option to opt-out of these cookies. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction.
Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction namely system level, top level and block level and can be incorporated in existing approaches.
After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results. This event accepted a total of 96 submissions selected from a submission pool of papers, from 12 different countries.
This event accepted a - tal of 42 submissions selected from a submission pool of 78 papers, from 9 d- ferent countries. This event accepted a total of 39 submissions selected from a subm- sion pool of 75 papers, from 6 different countries. Electronic System Level Design: an Open-Source Approach is based on the successful experience acquired with the conception of the ADL ArchC, the development of its underlying tool suite, and the building of its platform modeling infrastructure.
With more than accesses per year since , the dissemination of ArchC models reached not only students in quest of proper infrastructure to develop their research projects but also some companies in need of processor models to build virtual platforms using SystemC. The need to anticipate the development of hardware-dependent software and to build virtual prototypes gave rise to Transaction Level Modeling TLM.
It is the largest and oldest conference in reconfigurable computing and brings together academic researchers, industry experts, users and newcomers in an informal, welcoming atmosphere that encourages productive exchange of ideas and knowledge between the delegates. The fast and exciting advances in field programmable logic are increasing steadily with more and more application potential and need. New ground has been broken in architectures, design techniques, partial run-time reconfiguration and applications of field programmable devices in several different areas.
Many of these recent innovations are reported in this volume. The size of the FPL conferences has grown significantly over the years.
FPL in saw papers submitted. The technical program was assembled from 78 selected regular papers, 45 additional short papers and 29 posters, resulting in this volume of proceedings.
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